Pipeline processing device, clipping processing device, three-dimensional simulator device and pipeline processing method

ABSTRACT

An objective of this invention is to provide a pipeline processing device that enables the implementation of optimized pipeline processing and moreover has a simple configuration and control method, and a clipping processing device that uses this pipeline processing device. Data is sequentially transferred to pipeline register sections (500 to 506), but only when there is processing data in each previous stage, and given data processing is performed in data processing sections (520 to 524). After the end of input of processing data in which a plurality of data items is formed into one string D 0:3!, this data is automatically extracted from the pipeline register sections (500 to 506). These transfer and automatic extraction operations in the pipeline control sections (530 to 536) are controlled by an LD signal. This LD signal is formed by ENIN and FLASHIN signals.

TECHNICAL FIELD

This invention relates to a pipeline processing device as well as to aclipping processing device, a three-dimensional (3D) simulator device,and a pipeline processing method using such a pipeline processingdevice.

BACKGROUND OF ART

In the prior art, since real-time processing must be performed by a 3Dsimulator device, such as a 3D simulator device used in a video game orpiloting simulator for an aircraft or any of various other types ofvehicle that displays pseudo-3D images, data processing is generallyperformed by a method called pipeline processing.

In this case, pipeline processing is a data processing method in whichfunction-specific hardware is connected in series and the processingload is equalized between these components.

Processing devices using two methods, clock-driven pipeline processingand data-driven pipeline processing, are known as prior-art pipelineprocessing devices as shown in FIGS. 20A and 20B.

With the clock-driven pipeline processing device shown in FIG. 20A,registers 450 to 453 driven by a common clock signal are connected inseries, and data processing is performed thereby in data processingsections 455 to 458. This clock-driven pipeline processing device hasthe advantage that, since the entire flow of the data to be processed issynchronized by this common clock signal and is at the same timing, thecontrol method is extremely simple.

With the data-driven pipeline processing device shown in FIG. 20B,registers 460 to 463 that are driven only if there is processing data inthe previous stage are connected in series, and data processing isperformed thereby in data processing sections 465 to 468. In thisdata-driven pipeline processing device, each of the registers 460 to 463is driven only if there is processing data in the previous stage.Therefore, there must be processing data in all of the registers duringthe execution of pipeline processing. As a result, equalization of theload of data processing, which is an objective of pipeline processing,can be implemented even more efficiently.

However, both the above described clock-driven pipeline processingdevice and data-driven pipeline processing device have problems, asdescribed below.

With the clock-driven pipeline processing device, a common clock signalis supplied to all of the registers 450 to 453 and the processing datais transferred thereby. This means that the transfer of processing datawill continue, even if there is no processing data in the previous-stageregister. As a result, if there is a register to which processing datahas not been input, the presence of a register without processing datais noted during the pipeline processing, and it becomes impossible toimplement equalization of the load of data processing, which is theobjective of pipeline processing.

The description now turns to the data-driven pipeline processing device,but first deals with the defect that the control and configurationmethods thereof are not very simple. In other words, the device of thismethod must be provided with a control circuit for controlling the flowof processing data such that it proceeds onward only if there isprocessing data in the previous stage. However, when such a controlcircuit is provided, decisions as to what configuration and controlmethod to use are not easy problems to solve. To ensure that thiscontrol circuit can be connected to all the registers 460 to 463 andreduce the load on the hardware, it is necessary to make theconfiguration thereof as simple as possible and reduce the number ofcircuits, but these points cause major technical problems.

The flow of a data-driven pipeline processing device can only proceedforward if there is data in the previous stage. Therefore, processingdata in the register 461 can only be transferred to the data processingsections 466, 667, and 468 and the registers 462 and 463 of the nextstages if there is processing data in the register 460. Therefore, ifthe need arises to transfer data from the register 461 to the nextstage, regardless of the state of the previous stage, it becomesimpossible to implement an increase in the efficiency of the pipelineprocessing, and it also becomes impossible to implement optimization ofthe processing time of the overall device.

Thus, a clock-driven pipeline processing device has the advantage of asimple control method, but it also has a disadvantage in that it isdifficult to implement equalization of the pipeline processing.Conversely, a data-driven pipeline processing device has the advantageof enabling implementation of a certain amount of equalization of thepipeline processing, but it has the disadvantages that the controlmethod thereof is not simple and, in some cases, it becomes impossibleto optimize the pipeline processing overall. Therefore, it is desirableto have a pipeline processing device that provides the advantages ofboth types of pipeline processing, such as a pipeline processing devicecapable of mixing these two pipeline processing methods.

DISCLOSURE OF THE INVENTION

This invention was devised in the light of the above described problemsand has as its objective the provision of a pipeline processing devicethat enables the implementation of optimization of pipeline processingand that also has a simple configuration and control method, as well asa clipping processing device and pipeline processing method that use thepipeline processing device of this invention.

In order to achieve the above objective, a first aspect of thisinvention concerns a pipeline processing device for transferringprocessing data by pipeline processing, comprising:

a plurality of pipeline registers for sequentially transferringprocessing data in which a plurality of data items are formed into onestring; and

a pipeline control means to which a pipeline drive signal and a flashsignal are input, for controlling data transfer in the pipelineregisters on the basis of the pipeline drive signal and the flashsignal;

wherein each of the pipeline control means comprises:

means for permitting data transfer to one pipeline register among theplurality of pipeline registers only when there is processing data in apipeline register in a stage previous to the one pipeline register, whenthe pipeline drive signal has been enabled; and

means for automatically extracting from the plurality of pipelineregisters one string of processing data that has already been input,when the flash signal has been enabled, regardless of whether thepipeline drive signal is enabled or disabled.

In accordance with this aspect of the invention, processing data istransferred only when there is processing data in the previous stage,and processing data in which a plurality of data items are formed intoone string can be automatically extracted after the input thereof hasended, by enabling the flash signal. In other words, since data transferis always performed only when there is processing data in the previousstage when a pipeline drive signal is enabled (asserted), the pipelineprocessing load is equalized and processing can be made faster. On theother hand, processing data for which input has ended can beautomatically extracted by enabling the flash signal, regardless ofwhether or not there is processing data in the previous stage, thusenabling the processing data to be used rapidly by the next process. Asa result, this invention provides the optimal pipeline processing devicefor image calculation processing that particularly requires real-timecalculation processing, such as in a clipping processing device.

A second aspect of this invention concerns a pipeline processing devicefor transferring processing data by pipeline processing, comprising:

a plurality of pipeline registers using a transfer clock to sequentiallytransfer processing data in which a plurality of data items are formedinto one string; and

a plurality of pipeline control means, each connected to one of theplurality of pipeline registers, for generating and outputting a signalthat enables data transfer to the connected pipeline register, using thetransfer clock,

wherein each of the pipeline control means comprises:

a pipeline drive permitting means for generating a signal that permitsdata transfer to a pipeline register to which a pipeline control meansis connected, when either an input pipeline drive signal or input flashsignal that is input from a previous-stage pipeline control means hasbecome enabled, and also holding the input pipeline drive signal in afirst memory means, and enabling an output pipeline drive signal that isoutput to a subsequent-stage pipeline control means, when both an inputpipeline drive signal held at previously permitted data transfer in thefirst memory means and the input pipeline drive signal from theprevious-stage pipeline control means are enabled; and

a flash permitting means for holding the input flash signal that isinput from the previous-stage pipeline control means in a second memorymeans and enabling an output flash signal that is output to thesubsequent-stage pipeline control means, when either an input flashsignal that was held in the second memory means one transfer clockperiod previously or the input flash signal from the previous-stagepipeline control means is enabled.

This aspect of the invention first of all implements data-drivenpipeline processing as described below. When an input pipeline drivesignal of the first-stage pipeline control means is enabled (forexample, set to 1), data transfer to the first-stage pipeline registeris permitted and also 1 is stored in the first-stage first memory means.If the input pipeline drive signal then becomes 1, both the previous andcurrent input pipeline drive signals of the first-stage pipeline controlmeans are 1, and thus the output pipeline drive signal also becomes 1.This permits data transfer to the second-stage pipeline register. Asdescribed above, this invention ensures that processing data istransferred only when there is processing data in the previous stage,thus implementing data-driven pipeline processing.

On the other hand, automatic extraction of processing data is alsoimplemented by this invention. When the input flash signal of thefirst-stage pipeline control means becomes 1, all of the input flashsignals of the second stage onward become 1, and thus data transfer ispermitted for all of the pipeline registers. This input flash signal isheld in the second memory means. This enables the output flash signalfor one transfer clock period longer at each stage, so that thefirst-stage output flash signal is enabled for at least one transferclock period and the second-stage one is enabled for at least twotransfer clock periods. Thus, all of the processing data that is in thepipeline registers at the point at which the flash signal is enabled canbe automatically extracted.

In a third aspect of this invention, the pipeline drive permitting meanscomprises means for clearing data held in the first memory means,wherein initialization of the pipeline processing device is performed bythe data clearing means clearing the data held in the first memorymeans.

In accordance with this aspect of the invention, the data held in thefirst memory means is cleared by the data clearing means. This enables areturn to an initial state in which no processing data, which is to besubjected to data-driven pipeline processing, has been input. In thiscase, all the data that is already in the pipeline registers can beautomatically extracted while new data is input to the pipelineregisters, by, for example, enabling both the clear signal and the flashsignal.

A fourth aspect of this invention concerns a clipping processing devicefor performing clipping processing using a plurality of clippingsurfaces with respect to a three-dimensional object that is representedby a plurality of polygons, comprising:

inside/outside decision means for determining whether or not a polygonis divided by a clipping surface, on the basis of input polygon imagedata;

interior-division-point calculation means for using the input polygonimage data to calculate interior division points for the polygon, whenthe inside/outside decision means determines that the polygon isdivided; and

output control means for generating a pipeline drive signal and a flashsignal and outputting the signals to the interior-division-pointcalculation means;

wherein the interior-division-point calculation means comprises:

a plurality of pipeline registers for sequentially transferring polygonimage data in which a plurality of data items are formed into onestring; and

pipeline control means to which the pipeline drive signal and the flashsignal are input from the output control means, for controlling datatransfer in the pipeline registers on the basis of the pipeline drivesignal and the flash signal;

wherein each of the pipeline control means comprises:

means for permitting data transfer to one pipeline register among theplurality of pipeline registers only when there is polygon image data ina pipeline register in a stage previous to the one pipeline register,when the pipeline drive signal has been enabled; and

means for automatically extracting from the plurality of pipelineregisters one string of polygon image data that has already been input,when the flash signal has been enabled, regardless of whether thepipeline drive signal is enabled or disabled.

In accordance with this aspect of the invention, theinterior-division-point calculation processing of the clippingprocessing device can implement a pipeline processing method thatenables data-driven pipeline processing and also enables automaticextraction by the flash signal. Since the polygon image data used in aclipping processing device is an extremely long data string in which aplurality of data items are grouped together, the clipping processingmethod of this invention is extremely effective for such data.

In a fifth aspect of this invention, the interior-division-pointcalculation means comprises a division means for performing a divisionthat divides a distance between vertex coordinates of a polygon; and

the output control means comprises means for detecting completion of adivision performed by the division means and means for enabling thepipeline drive signal when division completion has been detected by thedetection means.

With this invention, division processing by the interior-division-pointcalculation means takes the most time, and it is impossible forsubsequent data processing until the result of this division processingis output. In such as case, the interior-division-point calculationprocessing is performed by the data-driven pipeline method. In otherwords, the output control means enables the pipeline drive signal afterdetecting division completion, to cause the polygon image data withinthe pipeline registers to be shifted one stage forward. On the otherhand, when interior-division-point calculation processing ends for onestring of polygon image data, the polygon image data is automaticallyextracted by enabling the flash signal, regardless of whether thepipeline drive signal is enabled or disabled, in other words, withoutwaiting for the division means to complete the division, implementing anincrease in the processing speed.

A sixth aspect of this invention further comprises means forre-inputting polygon image data for which clipping processing using oneclipping surface has ended to the inside/outside decision means and theinterior-division-point calculation means, and thus subjecting thepolygon image data to clipping processing using another clippingsurface.

This aspect of the invention makes it possible for clipping processingto be performed for a plurality of clipping surfaces by a singleclipping processing device, and also enables perspective projectionconversion processing. Since this invention enables the automaticextraction of one string of polygon image data by the flash signal,polygon image data that has been subjected to clipping processing inaccordance with one clipping surface can be immediately subjected toclipping processing by another clipping surface, thus enabling theimplementation of an increase in the processing speed.

A seventh aspect of this invention concerns a three-dimensionalsimulator device comprising the above clipping processing device andfurther comprising:

image synthesis means for synthesizing a field-of-view image as seenfrom an observer within a virtual three-dimensional space, using apolygon that has been subjected to clipping processing by the clippingprocessing device.

In accordance with this aspect of the invention, the number of polygonsthat must be handled by the image synthesis means can be greatly reducedby performing clipping processing by a clipping processing device,enabling the provision of a three-dimensional simulator device that iscapable of real-time image synthesis.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a preferred example of the pipelineprocessing device according to this invention;

FIG. 2 is a block diagram of an example of the pipeline registersection;

FIG. 3 is a block diagram of an example of the pipeline control section;

FIG. 4 is a table for illustrating the basic operation of to thisembodiment;

FIG. 5 is a table for illustrating the distinctive operation of thisembodiment;

FIG. 6 is a timing chart of the basic operation of this embodiment;

FIG. 7 is a timing chart of the distinctive operation of thisembodiment;

FIG. 8 is a timing chart of the state of the flash signal in the nextstage after the flash signal is asserted;

FIG. 9 illustrates the concept of a 3D simulator device to which thisembodiment is applied;

FIG. 10 is a schematic block diagram of an example of the 3D simulatordevice to which this embodiment is applied;

FIG. 11 illustrates the image processing calculations performed by the3D calculation section;

FIG. 12 illustrates the concept of texture mapping;

FIGS. 13A and 13B show an example of the format of data handled by the3D simulator device;

FIG. 14 is a schematic diagram for illustrating the clipping calculationmethod used in the clipping processing device;

FIG. 15, 15A and 15B are a block diagram of the concrete circuitconfiguration of the clipping processing device;

FIGS. 16A, 16B, and 16C are schematic illustrative diagrams of theclipping processing device used in self-loop mode;

FIGS. 17A, 17B, 17C, and 17D are schematic diagrams for illustrating theoperation of the clipping processing device;

FIGS. 18A and 18B are schematic diagrams for illustrating the operationof the clipping processing device;

FIGS. 19A, 19B and 19C are schematic diagrams for illustrating theoperation of the clipping processing device; and

FIGS. 20A and 20B are schematic block diagrams of a prior-artclock-driven pipeline processing device and data-driven pipelineprocessing device, respectively.

BEST MODE FOR CARRYING OUT THE INVENTION

1. Description of Pipeline Register Section and Pipeline Control Section

A block diagram of an example of the pipeline processing deviceaccording to this invention is shown in FIG. 1. As shown in this figure,the pipeline processing device of this invention comprises pipelineregister sections 500 to 506 and pipeline control sections 530 to 536.Data to be processed is supplied to data processing sections 520 to 524.

The pipeline register sections 500 to 506 each have the function ofstoring the processing data that is to be subjected to pipelineprocessing, and, to simplify the description, a case in which 4-bit datais subjected to pipeline processing is shown in FIG. 1. In other words,4-bit input data D 0:3! is input to each of the pipeline registersections 500 to 506, and the subsequent-stage data processing sectionoutputs output data Q 0:3!. Note, however, that the data processingsections 520 to 524 do not perform any data processing-if the data isshifted without modification, the output data Q 0:3! will be input as isto the subsequent-stage pipeline register.

The transfer of data in the pipeline register sections 500 to 506 isperformed by a clock signal BCLK that acts as a transfer signal.However, this data transfer by the clock signal BCLK is enabled onlywhen transfer is permitted by a transfer permitting signal LD. Thistransfer permitting signal LD is generated by the pipeline controlsections 530 to 536.

The pipeline control sections 530 to 536 have the function ofcontrolling the pipeline processing of data in the pipeline registersections 500 to 506. This control is performed by generating thetransfer permitting signal LD, then enabling or disabling the datatransfer in the pipeline register sections 500 to 506 by this signal.

To each of the pipeline control sections 530 to 536 is input the clocksignal BCLK for providing clock synchronization, an input pipeline drivesignal ENIN for performing pipeline drive, and an input flash signalFLASHIN for performing a flash operation. The transfer permitting signalLD, an output pipeline drive signal ENOUT, and an output flash signalFLASHOUT are generated from these input signals. The transfer permittingsignal LD is output to the pipeline register sections and data transferis enabled or disabled thereby. The output pipeline drive signal ENOUTand output flash signal FLASHOUT are input as the input pipeline drivesignal ENIN and input flash signal FLASHIN, respectively, to thesubsequent-stage pipeline control section.

Note that a RST signal is input to the pipeline register sections 500 to506 and the pipeline control sections 530 to 536, to perform aninitialization reset at power-on. A signal that is the inverse of aCLEAR signal (hereinafter expressed as the *CLEAR signal) is input tothe pipeline control sections 530 to 536, to enable the clearing of thecontents of the pipeline control sections 530 to 536 at a preferredtiming during data processing. This makes it possible to re-execute dataprocessing by first clearing the control details for the processing ofdata that has been sequentially stored in the pipeline control section,then using the initial-state control details.

Details of the configuration of the pipeline register sections 500 to506 are shown in FIG. 2. As shown in this figure, each of the pipelineregister sections 500 to 506 is comprises pipeline registers 510 to 516for holding or transferring data and a NAND circuit 518 that generates atransfer clock RCLK for these pipeline registers 510 to 516.

The input data D 0:3! is input to the pipeline registers 510 to 516, itis held in accordance with the transfer clock RCLK, and is transferredto the subsequent stage as the output data Q 0:3!.

The transfer permitting signal LD and the clock signal BCLK are input tothe NAND circuit 518. The clock signal BCLK is valid only when thetransfer permitting signal LD is 1, whereupon the transfer clock RCLK isgenerated. This enables or disables data transfer.

Details of the configuration of the pipeline control sections 530 to 536are Shown in FIG. 3. As shown in this figure, each of the pipelinecontrol sections 530 to 536 comprises a flash permitting section 540 anda pipeline drive permitting section 550. Note that an inverter circuit546 is provided to generate a signal that is the inverse of the clocksignal BCLK (hereinafter expressed as *BCLK).

The flash permitting section 540 has the function of generating theoutput flash signal FLASHOUT from the input flash signal FLASHIN, andcomprises a register 542 and an 0R circuit 544. The input flash signalFLASHIN is held in the register 542 in synchronization with the *BCLKsignal, then it is output to the OR circuit 544. If either the FLASHINsignal or the data stored in the register 542 is enabled (if it is 1),the OR circuit 544 enables the FLASHOUT signal. This FLASHOUT signalbecomes the FLASHIN signal for the subsequent-stage pipeline controlsection, and acts as a signal that enables the flash operation of thesubsequent stage.

The pipeline drive permitting section 550 is comprises a selector-drivenregister (register with selector) 552, AND circuits 556, 558, and 560,and an OR circuit 554.

The LD signal is generated by the OR circuit 554 if either the inputpipeline drive signal ENTN or the input flash signal FLASHIN is enabled(if it is 1) and is output to the pipeline register section and the ANDcircuit 556. This causes the pipeline drive of the pipeline registersection in this stage to be permitted.

The data input to a DA pin is held by the selector-driven register 552if an SA pin thereof is at 1, or the data input to a DB pin thereof isheld if the SA pin is at 0. An output of the AND circuit 556 is input tothis SA pin and the LD and CLEAR signals are input to this AND circuit556. The ENIN signal is input to the DA pin. An output of the ANDcircuit 558 is input to the DB pin and an output of the selector-drivenregister 552 and the *CLEAR signal are input to this AND circuit 558.

This configuration ensures that both the SA and DB pins become 0 if the*CLEAR signal is 0, and the data stored in the selector-driven register552 is thus cleared.

If either the ENIN signal or the FLASHIN signal becomes 1 and the LDsignal becomes 1, the SA pin goes to 1, the contents of the ENIN signalare stored, and the data stored the selector-driven register 552 isupdated. Conversely, the LD signal becomes 0, the data output from theselector-driven register 552 is fed back to the input thereof, and thusthe previous stored data is held.

If both the ENIN signal and the output of the selector-driven register552 are 1, in other words, if the data in both the previous-stagepipeline register section and the pipeline register section of thisstage is enabled, the output pipeline drive signal ENOUT is enabled.This ENOUT signal becomes the ENIN signal for the subsequent-stagepipeline control section, and acts as a signal that enables the pipelinedrive of the subsequent stage.

The operation of the pipeline processing device of this invention willnow be described using FIG. 4 and FIG. 5. The basic operation of thepipeline processing device of this invention is shown in FIG. 4. A1, A2,A3, . . . An represent items of actual processing data stored in thepipeline register sections 500 to 506. As shown in this figure, if theENIN signal is in an active state (1), transfer by that pipelineregister section is enabled and the data stored in the pipeline registersection is transferred to subsequent stages, one stage at a time. Forexample, the ENIN signal becomes 1 at a time 1 in this figure, theprocessing data A1 is input to the first-stage pipeline register sectionat a next time 2. In the same manner, since the ENIN signal is 1 attimes 3 and 4, the processing data A2 and A3 is input to this device attimes 4 and 5, respectively, and the already-input processing data issequentially shifted to subsequent stages.

After the end of the input of processing data A1 to A3 wherein aplurality of data items is formed into one string, as shown in thisfigure, the FLASHIN signal goes to an active state (1). The thus-inputprocessing data A1 to A3 is automatically extracted, regardless of theENIN signal. In the example shown in FIG. 4, the FLASHIN signal goes to1 at a time 6. This causes the processing data A1 to A3 to besequentially transferred to subsequent stages in synchronization withthe clock signal BCLK from a time 7, thus causing it to be automaticallyextracted.

The distinctive operation of the pipeline processing device of thisinvention is further illustrated in FIG. 5. Since the ENIN signalbecomes 1 at times 1, 3, and 4, processing data A1 to A3 is input atthose times. At the time 6, the ENIN and FLASH signals become 1simultaneously. This means that the next processing data B1 can be inputto the pipeline processing device at the same time that the input of theprocessing data A1 to A3 ends. Therefore, the processing data B1 isinput to the first stage at the time 7. The processing data A3 is alsotransferred to the second stage. At the time 7, the ENIN signal is nolonger in the active state. Therefore, the processing data B1 is held asis in the first stage at a time 8. In contrast thereto, since theprocessing data A1 to A3 has already been driven once by the FLASHsignal, it is sequentially shifted to subsequent stages insynchronization with the clock signal BCLK, regardless of state of theENIN signal, and is thus automatically extracted to the outside.

Since the pipeline processing device of this invention has the abovedescribed characteristic, there is no necessity for the previous-stagecontrol section that controls this device to provide further controlover this processing data, beyond simply setting the FLASH signal to 1after the output of the processing data has ended. Therefore, theprevious-stage control section that controls this device need onlycontrol the next processing data to be output. As a result, the circuitconfiguration can be made extremely simple, the size of the circuitrycan be made extremely small, and also, since it is no longer necessaryto design complicated control circuitry, a shortening of the designperiod can be planned.

2. Application to Clear Operation

To clear the pipeline processing details and re-execute the pipelineprocessing anew in a prior-art pipeline processing device, it isnecessary to clear the entire contents of the pipeline registersections. If the contents recorded in the pipeline register sections arecompletely cleared in this manner, the data stored in the pipelineregister sections before the clear operation will be lost. However,depending on circumstances, it is possible that it is desired to enablethis stored data as is, and clear only the pipeline processing details.In such a case, a method has been considered in which, for example,dummy data is input to the head of the pipeline register sections topush out the necessary data, but this necessitates wasted operations andtime. With the pipeline processing device of this invention, theprocessing data within the pipeline register sections remains valid andonly the pipeline processing details are cleared in such a case, sothat, after the clear, new data can be input immediately and thepipeline processing can be re-executed. The operation of the pipelineprocessing device of this invention in such a case is described below.

The timing of the basic operation of the pipeline processing device ofthis invention, shown in FIG. 6, will first be described. This operationis one in which the FLASH signal is not input at all.

At a time 1, the *CLEAR signal is negated, enabling preparation for theinput of processing data. In this case, "negate" means that the signalis changed from a logically active state to a state in which it is notactive.

Next, at a time 2, the ENIN signal is asserted by the previous-stagepipeline control section, to indicate that processing data has arrivedin the previous-stage pipeline register section. In this case, "assert"means that the signal is changed from a state in which it is notlogically active to an active state. If the ENIN signal is asserted inthis manner, the LD signal is asserted by the OR circuit 554 shown inFIG. 3 and processing data is fetched into the pipeline register sectionof this stage. However, since there is no valid data in this stage atthe time 2, the ENOUT signal that outputs to the subsequent stage is notasserted. In other words, the ENIN signal that indicates whether or notthe previous-stage processing data is valid is asserted but the outputof the selector-driven register 552 that indicates whether or not theprocessing data of this stage is valid is not asserted, so that theoutput of the AND circuit 560 is not asserted either.

Next, the ENIN signal is asserted at a time 3, so that processing datais input from the previous stage. In this case, information that theprocessing data for this stage is valid has already been stored in theselector-driven register 552 at the time 2. Therefore, the output of theselector-driven register 552 is asserted and the output of the ANDcircuit 560 is asserted. As a result, the ENOUT signal is output fortransferring the this-stage data to the next stage.

At a time 4, processing data is not input from the previous stage andthe ENIN signal is not asserted. Therefore, the ENOUT signal that is theoutput of the AND circuit 560 is not asserted.

The ENIN signal is again asserted at a time 5, and this causes the ENOUTsignal to be asserted immediately. This point differs from the abovedescribed time 2 in that the ENOUT signal is immediately asserted. It isbecause the output of the selector-driven register 552 indicatingwhether or not the processing data of this stage is valid has alreadybeen asserted at the time 5.

At a time 8, the *CLEAR signal is asserted and this clears all thepipeline registers section 500 to 506 again.

New processing data is input from a time 10.

When the *CLEAR signal was input at the time 8, the processing data ofthis stage and the processing data of the stages other than this stagewas being held so that this processing data would be lost. Therefore,all this processing data must be output before the clear operation. Onemethod that could be considered for performing this is to load data intothe initial-stage pipeline register section to act as dummy data, andthus push out the necessary processing data. However, this methodnecessitates the leading of unnecessary data, which is time-consumingand makes the control complicated. The pipeline processing device ofthis invention is designed to use the FLASH signals (the FLASHIN signaland FLASHOUT signal) in such a case. A timing chart of signals,including these FLASH signals, is shown in FIG. 7.

FIG. 7 differs from FIG. 6 in that the FLASHIN signal is also assertedat the same time that the *CLEAR signal asserted. If the FLASHIN signalis asserted, the LD signal also asserted by the OR circuit 554, so thatthe previous-stage processing data is transferred to the subsequentstage and is stored therein. This FLASHIN signal is also stored by theregister 542 and the design is such that a two-clock long FLASHOUTsignal is output. The time during which the FLASHOUT signal is assertedis increased by one clock for each subsequent stage, as shown in FIG. 8.

This enables the pipeline register sections after this stage to extractall of the processing data up until this stage. In this case, theselector-driven register 552 to which the ENIN signal is input iscleared by the *CLEAR signal. Therefore, the LD signal is asserted onlywhen there is once again processing data in the previous stage, evenwhile the flash operation is being performed and processing data beingautomatically extracted (time 10 in FIG. 7). More accurately, thepipeline control section of this stage can operate at a time 9 inexactly the same manner as usual, since the initialization has alreadyended at that point. The next-stage pipeline control section alsoreturns to normal operation at the time 10. Similarly, the next-stagepipeline control section can also return to the normal state at a time11. This illustrates that normal operation can be ensured from the time9 for the pipeline processing device of this invention, even whenprocessing data is input at usual continuously to the first stage. Thisenables pipeline processing on the input processing data in the previousstage in the usual manner after the clear operation, while performing aFLASH operation whereby processing data remaining in the pipelineregister section of the subsequent stage is automatically extracted.

3. Application to Clipping Processing

The description below concerns an example of the application of thepipeline processing device of this invention to clipping processingduring image processing.

1) Description of Overall 3D Simulator Device

The overall configuration of a 3D simulator device to which the pipelineprocessing device of this invention is applied will first be described.

Various applications are known in the prior art as 3D simulator devicesused in, for example, 3D games or piloting simulators for aircraft orvarious vehicle. In a 3D simulator device of this type, imageinformation relating to a 3D object 300, shown in FIG. 9, is previouslystored in the device. This 3D object 300 represents a display objectthat a player (observer) 302 can see via a screen 306. Image informationof the 3D object 300 is subjected to perspective projection conversionon the screen 306 so that a pseudo-3D image (projected image) 308 isdisplayed on the screen 306. With this device, if the player 302performs an operation such as a rotation or translation using a controlpanel 304, given 3D calculation processing is performed on the basis ofa control signal thereof. A calculation is first performed to determinewhether there is a change in a factor such as the viewpoint position orline-of-sight direction of the player 302 or the position or directionof the moving vehicle in which the player 302 is seated. Next, acalculation is performed to determine how the image of the 3D object 300will appear on the screen 306 in response to this change in theviewpoint position and line-of-sight direction, or other change. Theabove calculation processing is performed in real time to follow theactions of the player 302. This enables the player 302 topseudo-experience a virtual 3D space in which a change in sceneryconcomitant with a change in the player's own viewpoint position andline-of-sight direction or a change in the position and direction of themoving vehicle can be seen in real time as a pseudo-3D image.

An example of the 3D simulator device of this invention is shown in FIG.10. Note that the description below proceeds on the assumption that the3D simulator device is applied to a 3D game.

As shown in FIG. 10, the 3D simulator device of this invention isconfigured of a control section 412, a virtual 3D space calculationsection 413, an image synthesis section 401, and a CRT 446.

The virtual 3D space calculation section 413 sets a virtual 3D space inaccordance with control signals from the control section 412 and a gamesprogram stored in a central processing section 414. In other words, itperforms calculations to determine what the position of the 3D object300 is and in what direction is it arranged.

The image synthesis section 401 comprises an image supply section 410and an image forming section 428. The image synthesis section 401performs image synthesis of a pseudo-3D image in accordance with settinginformation on a virtual 3D space from a virtual 3D space calculationsection 413.

3D objects that configure a virtual 3D space are represented by this 3Dsimulator device as polyhedrons divided into 3D polygons. For example,the 3D object 300 shown in FIG. 9 is represented as a polyhedron dividedinto 3D polygons (1) to (6) (polygons (4) to (6) are not shown in thefigure). Coordinates and accompanying data (hereinafter called verteximage information) for each vertex of these 3D polygons are stored in a3D image information memory section 416.

Various types of calculation such as rotation or translation withrespect to this vertex image information and various types of coordinateconversion such as perspective projection conversion are performed bythe image supply section 410 in accordance with setting information ofthe virtual 3D space calculation section 413. After the vertex imageinformation that has been subjected to this calculation processing hasbeen converted in line with a given sequence, it is output to the imageforming section 428.

Intra-polygon image information is calculated by the image formingsection 428 from polygon data such as vertex coordinates. This imageinformation is converted into RGB data by a palette and mixer circuit444, then an image is output from the CRT 446.

In the 3D simulator device of the above configuration, the image supplysection 410 performs the calculations described below.

Taking a driving game as an example, as shown in FIG. 11, 3D objects300, 333, and 334 representing objects such as a steering wheel, abuilding, and a billboard, which are read out from the 3D imageinformation memory section 416 are arranged in a 3D space expressed by aworld coordinate system (XW, YW, ZW). Subsequently, image informationrepresenting those 3D objects is subjected to coordinate conversion to aviewpoint coordinate system (Xv, Yv, Zv) based on the viewpoint of theplayer 302.

Next, a type of image processing that is called clipping processing isperformed. In this case, clipping processing is image processing wherebyimage information that is outside the field of view of the player 302(or outside the field of view of a window opening into the 3D space), inother words, image information that is outside a region bounded byclipping surfaces 1, 2, 3, 4, 5, and 6 (hereinafter called a displayregion 20), is excluded. The image information necessary for subsequentprocessing by this 3D simulator device is only the image informationthat is within the field of view of the player 302. This means that, ifany other information could be excluded, the load during subsequentprocessing could be reduced. Although there are objects in alldirections around the player 302, if it could be arranged such that onlythose of the objects that are within the field of view are processed,the quantity of data to be processed subsequently can be greatlyreduced, so that a 3D simulator device that performs read-time imageprocessing, in particular, executes only essential image processing.

This is described below in more detail with reference to FIG. 11. Imageinformation on an object outside the field of view of the player 302(outside the display region 20), such as the 3D object 334 representinga billboard that has moved out of the field of view and backwards, isexcluded. This exclusion processing is performed by determining whetheror not an object is within a display region for each of the clippingsurfaces 1 to 6, then excluding the object only if it is outside all ofthose surfaces.

In contrast thereto, for the 3D object 333 of a building or the likethat is on the boundary of the display region 20, the part thereof thatis outside the display region 20 is excluded, and only the part that iswithin the display region 20 is used in subsequent image processing. Theimage information of the 3D object 300 of the steering wheel or thelike, which is completely included within the display region 20, is usedas is in the subsequent image processing.

Finally, perspective projection conversion to the screen coordinatesystem (XS, YS) is performed only for objects within the display region20, then sorting processing is performed.

Note that image synthesis is performed by methods called texture mappingand Gourand shading in this 3D simulator to provide a higher qualityimage.

The concept of the texture mapping method is shown in FIG. 12.

In the prior art, to synthesize the image of a 3D object 332 havingpatterns such a checks or stripes, as shown in FIG. 12, the 3D object isdivided into 3D polygons (1) to (80) (3D polygons (41) to (80) are notshown in the figure) and image processing is performed with respect toall of these polygons, because painting out one polygon can only beperformed with one specified color. As a result, the number of polygonsrequired to synthesize a high-quality image with a complicated patternincreases greatly, and thus it becomes impossible to synthesize ahigh-quality image of this type.

With this 3D simulator device processing such as rotation, translation,coordinate conversion for perspective projection conversion, andclipping of the 3D object 332 is performed for each of 3D polygons A, B,and C configuring the surfaces thereof, (to be specific, each of thevertices of these 3D polygons) and the checked or striped pattern ishandled as a texture that is separated from the polygon processing. Atexture information memory section 442 is provided within the imageforming section 428 shown in FIG. 10, and image information (textureinformation) to be applied to each of the 3D polygons, such as a checkedor striped pattern, is stored therein.

The address in the texture information memory section 442 that specifiesthis texture information is given as texture coordinates VTX, VTY foreach vertex of each of the 3D polygons. More specifically, texturecoordinates (VTX0, VTY0). (VTX1, VTY1), (VTX2, VTY2), and (VTX3, VTY3)are specified for each vertex of polygon A shown in FIG. 12.

Texture coordinates TX, TY for all of the dots within the polygon areobtained by s processor section 430 within the image forming section 428from the texture coordinates VTX, VTY for each of these vertices.Texture information corresponding to the thus-obtained texturecoordinates TX, TY is read out from the texture information memorysection 442 and is output to the palette and mixer circuit 444. Thisenables the synthesis of a 3D object covered with a texture such aschecks or stripes, as shown in FIG. 12.

The 3D simulator device represents the 3D object 332 as a 3D polygonsolid as described above. Therefore the continuity of brightnessinformation at boundaries of each 3D polygon causes a problem. Forexample, if an attempt is made to represent a sphere by using aplurality of 3D polygons and the same brightness is set for all the dotswithin each 3D polygon, a state would occur in which the boundaries ofeach 3D polygon would not be represented as "rounded," although it isdesired to represent them as "rounded" in practice. The 3D simulatordevice of this invention avoids this problem by a method called Gourandshading. With this method, brightness information VBRI0 to VBRI3 foreach vertex is given for each vertex of the 3D polygons, as shown inFIG. 12, in a similar manner to that of the above described texturemapping method, and brightness information for all the dots in the 3Dpolygon is obtained by interpolation from the brightness informationVBRI0 to VBRI3 for each of these vertices when the image is finallydisplayed by the image forming section 428.

As described above, the 3D simulator device of this invention isconfigured to use texture mapping and Gourand shading methods to enablefast image processing of a high-quality image. Thus the polygon imageinformation is configured as a plurality of data items formed into onestring, such as vertex display coordinates, vertex texture coordinates,and vertex brightness information for each polygon. There is also objectdata that is common data for identical 3D objects and frame data that iscommon data for identical frames. An example of the data format thereforis shown in FIG. 13. However, a major technical problem concerns thequestion of how data, (which consists of a plurality of data itemsformed into one string, as shown in this figure) should be processedefficiently and appropriately within the image supply section 410.

Note that, in order to simplify the description below, vertex brightnessinformation items VBRI0 to VBRI3 are represented in FIG. 13 as I0 to I3;vertex texture coordinates VTX0 to VTY3 are represented as TX0 to TY3;and vertex coordinates VX0 to VZ3 are represented as X0 to Z3.

2) Description of Clipping Processing Device

A clipping processing device 420 for performing clipping processing isincorporated in the image supply section 410, as shown in FIG. 10. Thedescription below concerns this clipping processing device 420.

A. Clipping Processing Method

The clipping processing method of this embodiment will first bedescribed with reference to FIG. 14. This figure shows the clipping of apolygon 70 by a clipping surface 1. In this figure, V0=(X0, Y0, Z0),V1=(X1, Y1, Z1), V2=(X2, Y2, Z2), and V3=(X3, Y3, Z3) are vertexcoordinates of the polygon 70 and h(V)=aX+bY+cZ+d is the plane equationof the clipping surface 1.

Inside/Outside Decision for Each Set of Vertex Coordinates

Simultaneously with the input of polygon data, an inside/outsidedecision is executed to determine whether vertex coordinates V0 to V3are in a region outside the clipping surface 1 or in a region withinthat surface. For this purpose, the following calculations are firstperformed

    h(V0)=aX0+bY0+cZ0+d

    h(V1)=aX1+bY1+cZ1+d

    h(V2)=aX2+aX2+cZ2+d

    h(V3)=aX3+bY3+cZ3+d

According to the above calculations, Vn is determined to be in thedisplay region if h(Vn) is less than or equal to zero, or Vn isdetermined to be in the out-of-display region if h(Vn) is greater thanzero. In the example shown in FIG. 14, since h(V0) and h(V3) are bothgreater than 0, it is determined that V0 and V3 are in theout-of-display region, whereas, since h(V1) and h(V2) are less than orequal to 0, it is determined that V1 and V2 are in the display region.

Interior-Division-Point Calculation

For a polygon 72 in FIG. 14 for which it has been determined that allvertices are in the display region, the configuration is such that allvertices are supplied as is to the next process (such as clippingprocessing and/or perspective projection conversion for the next plane).For a polygon 74 for which it has been determined that all vertices arein the out-of-display region, all vertices are excluded from the nextprocess.

In contrast thereto, clipping points in other words, interior divisionpoints (divided points) Vk and vl, are obtained for the polygon 70 thathas been clipped by the clipping surface 1. Vertices V0 and V3 areexcluded from the subsequent processing, and interior division points Vkand Vl are made vertices of the polygon 70 instead and these are used inthe subsequent processing.

To obtain the interior division points Vk and Vl interior divisionratios tk and tl are obtained from the following equations:

    tk=(|h(V0)|)/(|h(V1)-h(V0)|)

    tl=(|h(V2)|)/(|h(V3)-h(V2)|)

These interior division ratios tk and tl are then used to obtain theinterior division points Vk and Vl from the following equations:

    Vk=V0+tk(V1-V0)

    Vl=V2+tl(V3-V2)

The above interior-division-point calculations were described withreference to an example of calculating the interior division points forvertex coordinates, but interfor division points for vertex texturecoordinates or vertex brightness information could also be obtained byclipping with this embodiment. Concerning the number of vertices of thepolygons, the above description used an example of polygons with fourvertices, but this embodiment is not limited thereto and it can beapplied to clipping processing for polygons having any number n ofvertices. In such a case, the above equations can thus be expressed bythe following general equation to obtain output data Wout:

    Wout=Wa+ti(Wb-Wa)

W: Clipping for any one of vertex brightness coordinates I0 to In;vertex texture coordinates TX0, TY0 to TXn, TYn; or vertex coordinatesX0, Y0, Z0 to Xn, Yn, Zn

a, b: Point numbers between two points that are to be clipped

ti: The interior division ratio at that point

B. Configuration and Operation of Clipping Processing Device

The above described inside/outside decisions and interior-division-pointcalculations of the clipping processing device 420 of this embodimentcould be performed by the pipeline processing device shown in FIG. 1, toimplement an increase in the speed of processing. A block diagram of anexample of the clipping processing device 420 to which the pipelineprocessing device of this invention is applied is shown in FIG. 15.

As shown in FIG. 15, the clipping processing device comprises an inputsection 272, an inside/outside decision section 210 configured of aplane equation calculation section 216 and a clipping specificationsection 218, a polygon data register 274, an output control section 220for controlling the pipeline processing device, aninterior-division-point calculation section 230 that actually calculatesthe interior division points, and an output multiplexer 260 for feedingthe output data back to the input section 212.

Data such as frame data, object data, polygon data (data has beenconverted into the viewpoint coordinate system), and data forcontrolling the pipeline processing device is sequentially input to theinput section 212. From this data, the data necessary for the clippingprocessing device is extracted and subjected to various forms of dataformat conversion.

For example, details of the monitor that is to display the image, suchas its angle and size, are extracted from the frame data, leading to theextraction of coefficients of the plane equations for performing theclipping. Data necessary for the processing of each object is alsoextracted from the object data. Further data, such as the vertexcoordinates, vertex texture coordinates, and vertex brightnessinformation of the polygons, is extracted from the polygon data, this issubjected to the necessary data format conversion, then the vertexcoordinates are output to the plane equation calculation section 216 andthe data such as the vertex coordinates, vertex texture coordinates, andvertex brightness information is output to the polygon data register214.

The data input from the input section 212, such as the vertexcoordinates, vertex texture coordinates, and vertex brightnessinformation, is sequentially stored in the polygon data register 214,then data (Wa, Wb) is output to the interior-division-point calculationsection 230 in accordance with specifications from the clippingspecification section 218.

An inside/outside decision is performed by the plane equationcalculation section 216 for each of the vertex coordinates Vn of thepolygons in accordance with the equation given below, as described abovewith respect to the calculation method. In this case, the coefficientsa, b, c, and d are set by the frame data.

    h(Vn)=aXn+bYn+cZn+d

According to the above calculations, Vn is determined to be in thedisplay region if h(Vn) is less than or equal to zero, or Vn isdetermined to be in the out-of-display region if h(Vn) is greater thanzero.

The results of the decisions obtained by the above described planeequation calculation section 216 are first stored as index data for eachpolygon vertex by the clipping specification section 218. For example,when it has been determined whether the polygon 70 shown in FIG. 14 aredivided between V0 and V1, and between V2 and V3, index data (0, 1) and(2, 3) is stored. The clipping specification section 218 specifies tothe polygon data register 214 the output of vertex coordinates, vertextexture coordinates, and vertex brightness information of the polygoncorresponding to this index data. In a similar manner, the clippingspecification section 218 also specifies to the output control section220 control over the interior-division-point calculation correspondingto this index data. In this case, h(Vm) and h(Vn) (hereinafter called hmand hn) that are calculated by the plane equation calculation section216 are output to the interior-division-point calculation section 230 bythe clipping specification section 218.

If it is determined that all the vertices of a polygon are outside thedisplay region, that polygon becomes a clipped-out polygon. In such acase, a specification that the image configuration data corresponding tothat polygon is to be completely invalidated is therefore output to thepolygon data register 214 and the output control section 220.Conversely, if all the vertices of a polygon are determined to be withthe display region, interior-division-point calculation is notnecessary, In that case, a specification that interior-division-pointcalculation is not to be performed on that polygon is output to thepolygon data register 214 and the output control section 220.

The output control section 220 controls the pipeline register sections500 to 506 (represented by "P" in FIG. 15) and the pipeline controlsections 530 to 536 (represented by "PC" in FIG. 15) in accordance withspecifications from the clipping specification section 218. This controlis provided by the ENIN and FLASHIN signals.

The interior-division-point calculation section 230 comprisesabsolute-value calculation sections 232 and 234, a division section 240,a subtraction section 242, a multiplication section 248, an additionsection 250, the pipeline register sections 500 to 506, and the pipelinecontrol sections 530 to 536.

The configurations of the pipeline register sections 500 to 506 and thepipeline control sections 530 to 536 are the same as those describedabove. Note that the BCLK, *CLEAR, and RST signals are omitted from FIG.15,

The values of both |hm-hn| and |hm| are calculated by the absolute-valuecalculation sections 232 and 234 from hm and hn output from the clippingspecification section 218, go then these values are output to thedivision section 240. The interior division ratio ti=|hm|/|hm-hn| iscalculated from this data by the division section 240 and it is outputto the multiplication section 248.

The value of (Wb-Wa) is calculated from the polygon data Wa and Wb thatis input from the polygon data register 214 through the pipelineregister sections 500 and 501 and it is output to the multiplicationsection 248 through the pipeline register section 502. Note that thesedata items Wa and Wb are not just polygon vertex coordinates they alsoinclude vertex texture coordinates and vertex brightness information.This is because this data will be necessary for the subsequent imageprocessing when the polygon is divided.

The value of ti(Wb-Wa) is then calculated from these values of ti and(Wb-Wa) by the multiplication section 248 and it is output to theaddition section 250 through the pipeline register section 504.

The following value is calculated by the addition section 250 from thevalue of ti(wb-Wa) input through the pipeline register section 504 andthe value of Wa input through the pipeline register sections 501, 503,and 505:

    Wout=Wa+ti(Wb-Wa)

Thus the interior division points are obtained.

The calculation result Wout obtained by the interior-division-pointcalculation section 230 is input to the output multiplexer 260 throughthe pipeline control section 506.

Usually, when clipping processing is performed, this clipping processingmust be performed by a plurality of clipping surfaces 1 to 6 for onepolygon, as shown in FIG. 11. This embodiment is formed in such a mannerthat this clipping processing by a plurality of clipping surfaces isperformed by one or a plurality of clipping processing devices, byperforming an internal loop operation. The output multiplexer 260 isprovided for setting the internal loop for this processing. Connectionswhen an internal loop of this type is formed are shown in FIG. 16A toFIG. 16C.

First of all, as shown in FIG. 16A, new data is input after data thathas been subjected to processing has been output, and the clippingprocessing by first clipping surfaces is performed. Subsequently, asshown in FIG. 16B, an internal loop connecting the input and output ofthe output multiplexer 260 is formed. This returns data that has beensubjected to clipping processing by the first clipping surfaces, to theinput, then clipping processing by next clipping surface is performed onthis returned data.

After clipping processing has been performed in this manner inaccordance with a previously determined sequence of clipping surfaces insequence, the internal loop is removed and data is output to the nextstage.

An example of the above described processing in which a plurality ofstages of this clipping processing device are provided is shown in FIG.16C. For example, clipping processing by a first three clipping surfacesis performed by a first-stage clipping processing device 420a, andclipping processing by the remaining three surfaces is performed by asecond-stage clipping processing device 420b. Note that a coordinateconversion section 418 in this figure is a block that converts thecoordinates of each polygon into the viewpoint coordinate system and anoutput format conversion section 421 is a block that converts the formatof each polygon that has been deformed into a polygonal shape by theclipping processing into a four-sided polygon, for example.

With this embodiment, the clipping processing of the clipping processingdevice is performed by pipeline processing using the pipeline registersections 500 to 506 and the pipeline control sections 530 to 536. Anexample of the distinctive operation of this embodiment is describedbelow.

First of all, data in the format shown in FIG. 13 is input to the inputsection 212. This input data could be data coming from a stage previousto the clipping processing device, or it could be a self-loop datathrough the output multiplexer 260.

After the thus-input data has been subjected to predetermined formatconversion in the input section 272, it is output to other blocks suchas the inside/outside decision section 210 and the polygon data register214. For example, the vertex coordinates (X0 to Z3) shown in FIG. 13,which are to be subjected to inside/outside decision calculation areoutput to the inside/outside decision section 210. Similarly, data suchas the vertex brightness information (I0 to I3), vertex texturecoordinates (TX0 to TY3), and vertex coordinates (X0 to Z3) is output tothe polygon data register 214.

An inside/outside decision is performed for this polygon by the planeequation calculation section 216 within the inside/outside decisionsection 210, using the thus-input vertex coordinates (X0 to Z3). If theresult of the inside/outside decision is such that clipping occursbetween vertices V0 and V1, and between V2 and V3, for example, the(0, 1) and (2, 3) index data is stored in the clipping specificationsection 218.

When the inside/outside decision of the inside/outside decision section210 ends, vertex brightness information, vertex texture information, andvertex coordinates are output by the polygon data register 214 in apredetermined format based on the above described index data. In thiscase, data in the format of (Wa, Wb)=(I0, I1), (I1, -), (I2, -), (I2,I3), (TX0, TX1), (TY0, TY1), (TX1, -), (TY1, -), (TX2, -), (TY2, -),(TX2, TX3), (TY2, TY3), (X0, X1), (Y0, Y1), (Z0, Z1), (X1, -), (Y1, -),(Z1, -), (X2, -), (Y2, -), (Z2, -), (X2, X3), (Y2, Y3), and (Z2, Z3),for example, is sequentially output to the pipeline register sections500 and 501. Note that "-" in this data means "don't care." The pipelineregister sections in this case are driven by the ENIN signal. The outputof hm and hn to the absolute-value calculation sections 232 and 234 bythe clipping specification section 218 is arranged to occur at the pointat which the data processing by the division section 240 with respect tothe previous polygon data has ended.

With the embodiment shown in FIG. 15, the data processing performed bythe division section 240 takes the most time-it could take 12 clocks,for example. Otherwise, the absolute-value calculation sections 232 and234, the subtraction section 242, the multiplication section 248, theaddition section 250 take only one clock each for data processing.Therefore, at the point at which the data output from the polygon dataregister 214 has been transferred to the pipeline register sections 502and 503, it goes into a halted state waiting for the result of thecalculation by the division section 240, as shown in FIG. 17A. In otherwords, at the state in which (I0, I1-I0) has been stored in the pipelineregister sections 503 and 502, ENIN is negated and pipeline processinghalts. After a given time has expired, the ENIN signal is asserted andpipeline processing restarts when the calculation result is output fromthe division section 240, causing the state shown in FIG. 178.

In this example, since there is no interior division point between thevertices V1 and V2, it is necessary to output I1, without performing anyinterior-division-point calculation. Therefore, in this case, ti, whichis the output of the division section 240 is set to zero. Since divisionby the division section 240 is not necessary, the contents of thepipeline register sections 500 to 506 shift in synchronization with theclock signal BCLK. This is the state shown in FIG. 17C.

In FIG. 17C, since ti has been set to zero by the state shown in FIG.17B, zero is input to the pipeline register section 504. Theinterior-division-point IK=I0+ti(I1-I0) of the vertices V0 and Vl, whichis the final calculation result is input to the pipeline registersection 506. Data (I2, -) is input to the pipeline register sections 503and 502. Since it is also necessary to output I2, without performing anyinterior-division-point calculation, ti is set to zero. In this state,the contents of the pipeline register sections 500 to 506 are shifted toproduce the state shown in FIG. 17D.

As shown in FIG. 17D, I1 is output to the pipeline register section 50without being subjected to any interior-division-point calculation. Data(I2, I3-I2) for obtaining the interior division point between thevertices V2 and V3 is input to the pipeline register sections 503 and502. By this sequential progress of the pipeline processing, the vertexbrightness information (I0, I1, I2, I3) for the polygon is convertedinto (IK, I1, I2, IL). In a similar manner, interfor-division-pointcalculation is performed for the vertex texture coordinates (TX0 to TY3)and vertex coordinates (X0 to Z3), to provide new polygon data after theclipping processing.

A state in which the final data (Z2, Z3) of this polygon is output fromthe polygon data register 214 is shown in FIG. 18A. At the end point ofthe input of data in which a plurality of data items is formed into onestring, the output control section 220 asserts the FLASHIN signal. Then,the data in which a plurality of data items is formed into one string isautomatically driven to be extracted, regardless of the pipeline drivein accordance with the ENIN signal. In other words, as shown in FIG.18B, regardless of the fact that the data to be processed next has notyet been input to the pipeline register sections 500 and 501, datadriven by this FLASHIN signal is automatically shifted to the nextpipeline register section. Brightness information (I0, I1) for thepolygon that is to be processed next is input to the pipeline registersections 501 and 500, as shown in FIG. 19A, and a state occurs in whichthe division result ti from the section 240 is output, as shown in FIG.19B. In this case too, data relating to the previous polygon isautomatically extracted, regardless of the output of the divisionresult, as shown in FIG. 19B and FIG. 19C.

With this embodiment as described above, there absolutely no necessityfor controlling data once it has been driven by the FLASHIN signal,making the control method extremely simple and enabling theimplementation of a shortening of the design period, as shown in FIG.19B and FIG. 19C. As a result, data for which calculation processing hasended can be used immediately in the next calculation processing.

This embodiment forms a self-loop as shown in FIG. 15 and FIG. 16, toreturn data for which calculation processing has ended to the inputsection 212 via the output multiplexer 260. The configuration is suchthat an inside/outside decision is performed for the next surface by theinside/outside decision section 210, using this returned data, andclipping processing is performed for the next surface. Thus, it isnecessary to return data for which the calculations by theinterior-division-point calculation section have ended to theinside/outside decision section 210 through the output multiplexer 260,as quickly as possible. However, in the pipeline processing deviceaccording to the prior-art data drive method, the next data is in astate in which it is waiting for the division result from the pipelineregister sections 502 and 503, as shown in FIGS. 19B and 19C, so thatthe data in the pipeline register sections 504, 505, and 506 cannotproceed further. This state means that efficient pipeline processingcannot be performed by the prior-art pipeline processing device, whichmakes it extremely inappropriate as a 3D simulator device thatnecessitates real-time pipeline processing.

In this case, special methods have been considered for avoiding thisstate, such as inputting dummy data to the pipeline register sections topush out the previous data. However, the timing of pipeline processingwithin this clipping processing device changes in a complicated manner,owing to various factors such as the player's control state and the gamestate; In other words, a state could occur in whichinterior-division-point calculation must be performed for virtually allof the polygons, depending on the player's control. Conversely, if thegame state specifies that the polygons are concentrated in the centralsection of the display screen, a state will occur in which there is noneed for interior-division-point calculation for virtually all of thepolygons. Another state could occur in which the processing of aprocessing section that is a previous stage of the pipeline processingdevice is delayed, in which case it will be unable to output data tothis pipeline processing device. Therefore, if the above states causesuch complicated changes in the timing of the clipping processing, itwould not be easy to use one of the above described special methods toavoid a loss of efficiency of the pipeline processing.

In contrast thereto, this embodiment makes it possible to performefficient pipeline processing by an extremely simple control method thatdrives the data in a pipeline by the ENIN signal then simply asserts theFLASHIN signal after the end of data input, even if the above describedvarious different states cause the timing of the clipping processing tochange in a complicated manner. Moreover, the configuration of thepipeline control sections 530 to 536, each connected to one of thepipeline register sections 500 to 506, is extremely simple, so that thenumber of circuits is very small. Therefore, the pipeline processingdevice of this embodiment is provided with both the advantages of adata-driven pipeline processing device that implements efficientpipeline processing and a clock-driven pipeline processing device thatbas a simple control method, so that it is the optimal pipelineprocessing device in a 3D simulator device where real-time pipelineprocessing is necessary.

Note that the present invention is not limited to the above describedembodiments; it can be embodied in many different ways within the scopeof the invention.

For example, the calculation processing of data to which this inventionis applied is not limited to the above described clipping processing andit could be applied to various other types of pipeline processing inwhich real-time calculation processing is necessary.

The input location of the input flash signal of this invention is notlimited to the first stage; it could be input to the second or thirdstage, for example.

The calculation method used in this invention for the clippingprocessing performed by the clipping calculation means is not limited tothe above described calculation method; calculation methods usingvarious different types of algorithm could be used instead.

The 3D simulator device of this invention can be applied to variousdifferent purposes, such as an arcade games machine, a family computer(domestic) games machine, a flight simulator, or a driving simulator asused in a driving school. It can also be applied to a large-scaleattraction type of game device or simulator in which a number of playersparticipate.

The calculation processing performed by components such as the virtual3D space calculation means, image synthesis means, and clippingprocessing device that have been described above with respect to thisembodiment could be performed by a dedicated (custom made) imageprocessing device, or it could be performed by software means such as ina general-purpose (standard type) microprocessor or DSP.

Furthermore, the calculation processing performed by the virtual 3Dspace calculation means and image synthesis means is not limited to thecalculations described with respect to this embodiment.

The 3D simulator device to which this invention is applied includes aconfiguration in which the image is displayed on a display means knownas a head-mounted display (HMD).

What is claimed is:
 1. A pipeline processing device for transferring processing data by pipeline processing, comprising:a plurality of serially connected pipeline registers for sequentially transfer which processing data in which a plurality of data items are formed into one string; and pipeline control means, to which a pipeline drive signal and a flash signal are input, for controlling data transfer in said plurality of pipeline registers on the basis of said pipeline drive signal and said flash signal, said pipeline control means comprising: means for permitting data transfer to one pipeline register among said plurality of serially connected pipeline registers from a previous serially connected pipeline register only when processing data is present in the serially connected pipeline register and said pipeline drive signal has been enabled; and means for automatically extracting from said plurality of serially connected pipeline registers one string of processing data that has already been input when said flash signal has been enabled, independently of said pipeline drive signal being enabled or disabled.
 2. A pipeline processing device for transferring processing data by pipeline processing, comprising:a plurality of serially connected pipeline registers using a transfer clock to sequentially transfer processing data in which a plurality of data items are formed into one string; and a plurality of pipeline control means, each connected to one of said plurality of serially connected pipeline registers, for generating and outputting a signal that enables data transfer to a pipeline register from a previous serially connected pipeline register using said transfer clock; wherein each of said pipeline control means comprises:pipeline drive permitting means for:generating a signal that transfers data to that pipeline register connected to the pipeline control means from a previous serially connected pipeline register connected to a pipeline control means when one of an input pipeline drive signal and an input flash signal input to the pipeline control means connected to said pipeline register from the pipeline control means connected to the previous serially connected pipeline register is enabled, and also holding said input pipeline drive signal in a first memory means of the pipeline control means connected to said pipeline register, and enabling an output pipeline drive signal to be output from the pipeline control means connected to said pipeline register to a pipeline control means connected to a subsequent serially connected pipeline register when both 1) an input pipeline drive signal held in said first memory means, and 2) said input pipeline drive signal input to the pipeline control means connected to said pipeline register from the pipeline control means connected to the previous serially connected pipeline register, are enabled; and flash permitting means for:holding the input flash signal input to the pipeline control means connected to said pipeline register from the pipeline control means connected to the previous serially connected pipeline register in a second memory means of the pipeline control means connected to said pipeline register, and enabling an output flash signal output from the pipeline control means connected to said pipeline register to the pipeline control means connected to the subsequent serially connected pipeline register when either an input flash signal held in said second memory means one transfer clock period previously or said input flash signal inputted to the pipeline control means connected to said pipeline register from the pipeline control means connected to the previous serially connected pipeline register is enabled.
 3. The pipeline processing device as defined in claim 2, wherein said pipeline drive permitting means comprises means for clearing data held in said first memory means and said data clearing means initializes said pipeline processing device by clearing said data held in said first memory means.
 4. A clipping processing device for performing clipping processing using a plurality of clipping surfaces with respect to a three-dimensional object represented by a plurality of polygons, comprising:inside/outside decision means for determining whether a polygon is divided by a clipping surface on the basis of input polygon image data; interior-division-point calculation means for using said input polygon image data to calculate interior division points for said polygon when said inside/outside decision means determines said polygon is divided; and output control means for generating a pipeline drive signal and a flash signal and outputting said pipeline drive and flash signals to said interior-division-point calculation means; wherein said interior-division-point calculation means comprises:a plurality of serially connected pipeline registers for sequentially transferring polygon image data in which a plurality of data items are formed into one string; and pipeline control means, to which said pipeline drive signal and said flash signal are input from said output control means, for controlling data transfer in said pipeline registers on the basis of said pipeline drive signal and said flash signal, said pipeline control means comprising:means for permitting data transfer to one pipeline register among said plurality of pipeline registers from a previous serially connected pipeline register only when polygon image data is present in the previous serially connected pipeline register and said pipeline drive signal has been enabled; and means for automatically extracting from said plurality of pipeline registers one string of polygon image data that has already been input when said flash signal has been enabled, independently of said pipeline drive signal being enabled or disabled.
 5. The clipping processing device as defined in claim 4, wherein:said interior-division-point calculation means comprises a division means for performing a division that divides a distance between vertex coordinates of a polygon; and said output control means comprises means for detecting completion of a division performed by said division means and means for enabling said pipeline drive signal when division completion has been detected by said detection means.
 6. The clipping processing device as defined in claim 4, further comprising:means for re-inputting polygon image data for which clipping processing using one clipping surface has ended to said inside/outside decision means and said interior-division-point calculation means, and thus subjecting said polygon image data to clipping processing using another clipping surface.
 7. A three-dimensional simulator device comprising a clipping processing device as defined in claim 4, further comprising:image synthesis means for synthesizing a field-of-view image as seen from an observer within a virtual three-dimensional space, using a polygon that has been subjected to clipping processing by said clipping processing device.
 8. A pipeline processing method comprising:using a pipeline drive signal and a flash signal to control data transfer between a plurality of serially connected pipeline registers, wherein a plurality of data items are formed into one string; which is input into the plurality of serially connected pipeline registers; permitting data transfer to a pipeline register from a previous serially connected pipeline register only when processing data exists in the previous serially connected pipeline register and said pipeline drive signal has been enabled; and automatically extracting one string of processing data that has already been input when said flash signal is enabled, independently of said pipeline drive signal being enabled or disabled. 